A pipelined A/D converter can be mentioned as a circuit using the sample hold circuit. As a pipelined A/D converter 10, for example, a circuit illustrated in FIG. 7 is known (for example, see PLT 1).
Such a pipelined A/D converter 10 is configured, as illustrated in FIG. 7, such that N stages of unit blocks 100 (1) to 100(N), from Stage1 to StageN, are made in cascade connection.
Since each of the unit blocks 100(1) to 100(N) has an identical configuration, the configuration of Stage1 (i.e., unit block 100(I)) will be described, herein.
As illustrated in FIG. 7, the StageI includes an SSH (i.e., Sub Sample Hold) circuit 101, an SADC (i.e., Sub AD Converter) circuit 102, a DAC (i.e., D/A Converter) circuit 103, and an adder 104.
The SSH circuit 101 of the StageI receives an analog output signal ResidueI−1 output from a unit block StageI−1 on a previous stage.
The SADC circuit 102 is provided for carrying out an A/D conversion on the analog output signal ResidueI−1 received by the SSH circuit 101 into a digital signal DigitalI. The digital signal DigitalI is output as an output signal (i.e., DigitalI) of the Stage1. It is to be noted that the digital signal DigitalI output from the SADC circuit 102 is summed with a digital signal DigitalI output from the SADC circuit 102 of each of the Stage1 to StageN, in a predefined rule. The result is output as a digital output signal representing an A/D conversion result.
The DAC circuit 103 generates an analog signal corresponding to the digital signal DigitalI from the SADC circuit 102, and outputs it to the adder 104.
The adder 104 subtracts the analog signal generated by the DAC circuit 103 from the analog signal received by the SSH circuit 101, and outputs the analog signal that is a subtraction result, as ResidueI which is a residue signal to a unit block StageI+1 on a subsequent stage. In this situation, the analog signal (i.e., ResidueI) as the residue signal which is obtained by subtraction at the adder 104 is amplified by a predefined multiplication, so that the A/D conversion is enabled by the identical unit block (i.e., Stage) configuration without increasing the demanded accuracy of the unit block StageI+1 on the subsequent stage. Hence, the A/D conversion with high accuracy is achieved.
In the meantime, the SSH circuit 101, the DAC circuit 103, and the adder 104 are generally configured with a combination of a single operational amplifier and a capacitance CAP. The circuit configured by combining the operational amplifier and the capacitance CAP is referred to as Multiplying DAC (i.e., MDAC: Multiplying Digital Analog Convertor) 105.
FIG. 8A and FIG. 8B are schematic configuration views illustrative of an example of the MDAC 105.
In FIG. 8A and FIG. 8B, FIG. 8A illustrates a circuit configuration in a sampling phase (i.e., Sampling Phase), and FIG. 8B illustrates a circuit configuration in a holding phase (i.e., Holding Phase). The MDAC 105 realizes the circuit of FIG. 8A in the sampling phase by selectively changing a switch, not illustrated, depending on a conversion clock signal CLK, and realizes the circuit of FIG. 8B in the holding phase. It is to be noted that a variable I of “CsI” in FIG. 8A means Cs included in the StageI.
As illustrated in FIG. 8A and FIG. 8B, the MDAC 105 includes a sampling capacitor CsI in which unit capacities each having the same size are combined in parallel to each other, an MDAC-AMP 11 configured with an operational amplifier, and a parasitic capacitance Cp present at an input end of the MDAC-AMP 11. The MDAC 105 operates to alternatively achieve the sampling phase (of FIG. 8A) and the holding phase (of FIG. 8B) depending on the conversion clock signal CLK to be input.
In the sampling phase (of FIG. 8A), an analog output signal ResidueI−1 of the unit block StageI−1 on the previous stage is charged in the sampling capacitor CsI. In other words, the analog output signal ResidueI−1 is input into one end of the sampling capacitor CsI, whereas the other end thereof is connected with an inverting input terminal of the MDAC-AMP 11. Then, the input end and output end of the MDAC-AMP 11 are short-circuited on the ground level. The parasitic capacitance Cp is similarly short-circuited to the ground level.
On the other hand, in the holding phase (of FIG. 8B), the output end of the MDAC-AMP 11 and an inverting input end thereof are connected through a capacitance Cf. Also, as to the capacitance Cr, each of plural unit capacitances included in the capacitance Cr is connected to anyone of “+Vr”, “zero”, or “−Vr” depending on the digital signal Digital′ output from the SADC circuit 102 of FIG. 7. In other words, one end of the capacitance Cr is connected to any one of “+Vr”, “zero”, or “−Vr”, whereas the other end is connected to the inverting input end of the MDAC-AMP 11.
The capacitance Cf and the capacitance Cr are each configured with a part of the plural unit capacitances included in the sampling capacitor CsI. In other words, as to the sampling capacitor CsI, in the holding phase, a part of the unit capacitances included in the sampling capacitor CsI is used as the capacitance Cf that connects the output end and the inverting input end of the MDAC-AMP 11, and the remaining unit capacitances are used as the capacitance Cr.
It is to be noted that, here, the description has been given of a case where a part of the plural unit capacitances included in the sampling capacitor CsI is used as the capacitance Cf and the capacitance Cr. However, this configuration is not always the case. For example, the plural unit capacitances included in the sampling capacitor CsI are used as the capacitances Cr without change, and the capacitance Cf may be provided separately.
The output from the MDAC-AMP 11 is connected to a sampling capacitor CsI+1 of an MDAC 105 configuring a unit block of StageI+1 on a subsequent stage, the output from the MDAC-AMP 11 of StageI is output to the sampling capacitor CsI+1 on the subsequent stage, as the analog output signal ResidueI. Also, a non-inverting input end of the MDAC-AMP 11 is kept on the ground level.
In this situation, when the DC (i.e., direct current) gain of the MDAC-AMP 11 is assumed to be “a0”, a voltage Va at the inverting input end of the MDAC-AMP 11 can be represented by following expression (1), by use of a voltage Vout at the output end of the MDAC-AMP 11.Va=−(1/a0)Vout  (1)
For example, in a case where all the voltages connected to the unit capacitances included in the capacitance Cr are zero, following expression (2) is satisfied from the law of conservation of charge accumulated in the capacitance in the sampling phase and holding phase.CsI×Vin=Cf(Vout−Va)+Cr(0−Va)+Cp(0−Va)  (2)
From the above expressions (1) and (2), the output ResidueI from the MDAC-AMP 11, namely the output Vout from the MDAC 105, in the holding phase, can be represented by following expression (3).Vout=(CsI/Cf)×{1/(1+1/(a0×f))}×Vin  (3)
Here, “a0” in the expression (3) represents the DC (i.e., direct current) gain of the MDAC-AMP 11, as described above. Also, “f” refers to feedback factor of the MDAC-AMP 11, and can be represented by following expression (4) by use of the respective capacitances Cr, Cf, and Cp.f=Cf/(Cr+Cf+Cp)  (4)
In a transfer function represented by the expression (3), when an input/output property is ideal, the expression (3) can be represented by following expression (5).Vout=(CsI/Cf)×Vin  (5)
From the expressions (3) and (5), in order to make the ideal input/output property available, it is understood that the DC Gain “a0” of the MDAC-AMP 11 has to be large enough to the infinity.
Actually, the DC Gain “a0” is increased according to the demanded accuracy.
In general, a multistage or cascode configuration is needed to increase the DC Gain of the AMP. Therefore, there arises a problem in that keeping a good stability is difficult or the output amplitude is subject to a limitation.
To solve such a problem, As a method of obtaining a high gain property without increasing the DC Gain “a0”, there is a technique called Summing Point Monitoring (hereinafter, referred to as SPM).
FIG. 9A and FIG. 9B are a specific example of achieving the SPM. FIG. 9A is a circuit configuration in the sampling phase, and FIG. 9B is a circuit configuration in the holding phase.
In this circuit, after a voltage Va at the Summing Point is sampled (added) at a capacitance Ce1 once, f′ is made available with a ratio of capacitances Ce1 and Ce2 by use of a feedback circuit of the AMP. In this example, Cp′ represents a parasitic capacitance present at the input end of a Gain-AMP 12.
FIG. 9C is another specific example of achieving the SPM (for example, see non-PLT 1).
In this circuit, the voltage is sampled at the capacitance Ce1, and is then transferred through the capacitance Ce2.